Question: I have zero foundation and want to learn FPGA. I want someone with experience to talk about where I should start, what tutorials should I read, what learning boards and development boards should be used, what books to read, etc. I hope that experienced and kind people can Give me some guidance. If you want to make it fast, then watch the video online. This is mainly for the application. Let your board run within an hour. Getting up happily in the early stage, learning and applying it flexibly, is that there is no system theory support in the later stage, which will be a bit difficult, especially for large projects, which is completely tragedy. It can be done in China. I know Zhou Ligong, and Amy Electronics can do it too. Both of these have learning boards, but the latter's tutorial is copied from the former. The former has a more solid foundation, so buy the former if you don't have any shortage of funds. If you are quick, you must have a must-have for counting e-books. It is better to read and learn. You can buy the rest of the books in moderation. In fact, as long as you are interested, learn slowly, and it is not difficult to get started, you should go online shopping for the board. I have been to Huaqiangbei for many times, but there is no good board. Lots of online shopping! To summarize a few points 1. Look at the code and build a model Only by establishing logical models in my mind and understanding the basis of the realization of the internal logic structure of FPGA can we understand why the overall thinking of writing Verilog and C is different, and can understand the difference in the design methods of sequential execution languages ​​and parallel execution languages. . When you see a simple program, you should think of what kind of functional circuit it is. 2. Use mathematical thinking to simplify design logic Learning FPGA is not only important for logical thinking, but good mathematical thinking can also simplify your design. So, those children who have a headache when seeing high numbers need to pay attention to this course. To give a simple example, for example, there are two 32-bit data X[31:0] multiplied by Y[31:0]. Of course, both Altera and Xilinx have ready-made multiplier IP cores that can be called. This is also the simplest method, but two 32-bit multipliers will consume a lot of resources. So is there a way to save resources and achieve it in a less complicated way? We can make a slight modification: Split X[31:0] into two parts X1[15:0] and X2[15:0], let X1[15:0]=X[31:16], X2[15:0]=X[15 :0], then X1 is shifted by 16 bits to the left and added with X2 to get X; also, Y[31:0] is divided into two parts Y1[15:0] and Y2[15:0], let Y1[15: 0]=Y[31:16], Y2[15:0]=Y[15:0], Y1 is shifted to the left by 16 bits and then added to Y2 to get Y; then the multiplication of X and Y can be converted into X1 And X2 are multiplied by Y1 and Y2 respectively, so that a 32bit*32bit multiplication operation is converted into four 16bit*16bit multiplication operations and three 32bit addition operations. After the conversion, the occupied resources will be reduced a lot. If you are interested in children's shoes, you may wish to take a comprehensive look and see how much difference between the two. 3. The relationship between clock and flip-flop "The clock is the controller of sequential circuits" is too classic, and it can be said to be the holy word of FPGA design. The design of FPGA is mainly based on sequential circuits, because no matter how complicated the combinational logic circuit is, it will not change too much, and it will not be too difficult to understand. But the sequential circuit is different. All its actions are triggered by the clock rhythm. It can be said that the clock is the controller of the entire circuit. If the control is not good, the circuit function will be confused. For example, the clock is equivalent to the heart of the human body. Every time it beats, it triggers a CLK, which supplies blood to the various organs of the body and maintains the normal operation of the body. The normal functioning of each organ system is indispensable to the composition of tissue cells. Then trigger Organs can be compared to the basic unit tissue cells. The clock of the sequential logic circuit is the "motor" that controls the state transition of the sequential logic circuit. Without it, the sequential logic circuit cannot work normally, because the sequential logic circuit mainly uses the state of the flip-flop storage circuit, and the flip-flop state transition requires the rise of the clock. Or falling edge! This shows the core role of the clock in the sequential circuit! Finally, let's briefly talk about the experience. It boils down to more practice, more thinking, and more asking. Real knowledge is gained through practice. It is better to practice it yourself than to read other people’s plans 100 times. The motivation for practice comes from interest on the one hand, and pressure on the other. I personally think the latter is more important. There is a need to easily form pressure, which means that it is best to exercise in actual project development, rather than learning for the sake of learning. In the process of practice, you should think more about the reasons for the problem, and ask more why after the problem is solved. This is also the process of experience accumulation. If you have the habit of writing project logs, it is better to solve the problem and the cause. The methods are written in. Finally, I have to ask more. If you encounter a problem and think about it, you must ask if you can’t solve it. After all, personal power is limited. You can ask classmates and colleagues, search engines, and netizens. You can ask for an article or friends. It is possible to help oneself solve the problem quickly. Why do a large number of people find FPGA difficult to learn? 1. Not familiar with the internal structure of FPGA and basic principles of programmable logic devices Why is FPGA programmable? I'm afraid many rookies don't know, and they don't want to know. Because they think it is irrelevant. They subconsciously think that it is programmable, it must be like writing software. The idea of ​​software programming is deep-rooted, seeing Verilog or VHDL is like seeing C language or other software programming languages. Read one by one, analyze one by one. If these rookies always refuse to understand why FPGAs can be programmed, and do not understand the internal structure of FPGAs, it would be a fantasy to learn FPGAs. Although the EDA software is now very advanced, it can also synthesize something like writing software, but maybe only God knows what EDA software finally synthesizes. Maybe just light a lamp and run a horse. This is why many rookies are still rookies after learning N for a long time. So why can FPGA be "programmed"? First, let's understand what "cheng" is. Enlightenment "Cheng" is just a bunch of 01 codes with a certain meaning. Programming is actually writing these 01 codes. It's just that we now have a lot of development tool calculations or other operations. So the software is one by one. Usually, these 01 codes are not written directly, but written in a high-level language, and finally converted into this 01 code by the development tool. For software programming, the processor will have a special decoding circuit to translate these 01 codes into various control signals one by one, and then control its internal circuits to complete the reading one by one, because the operation of the software is completed step by step. The programming of FPGA essentially depends on these 01 codes to achieve its function changes, but the difference is that FPGAs can perform different functions, instead of relying on the 01 codes to be translated like software to control an arithmetic circuit, inside the FPGA Without these things. There are three main blocks inside FPGA: programmable logic unit, programmable wiring and programmable IO module. What is a programmable logic unit? Its basic structure consists of a 4-input or 6-input 1-output "truth table" made of a certain memory (SRAM, FLASH, etc.) plus a D flip-flop. Any combinational logic circuit with 4 inputs and 1 output has a corresponding "truth table". Similarly, if you use such a memory to make a "truth table" with 4 inputs and 1 output, you only need to modify its "truth table". The internal value can be equivalent to any combinational logic of 4 inputs and 1 output. What are the internal values ​​of these "truth tables"? It's just those 01 codes. What if you want to implement sequential logic circuits? This is not a D flip-flop, any sequential logic can be converted to a combinational logic + D flip-flop to complete. But after all, only a logic circuit with 4 inputs and 1 output is realized. Usually, the scale of the logic circuit is quite large. then what should we do? At this time, a programmable connection is needed. There are many link points controlled by memory on these lines. By rewriting the value of the corresponding memory, it is possible to determine which lines are connected and which lines are disconnected. This can combine many programmable logic units to form a large-scale logic circuit. Finally, there is the programmable IO, which is actually what FPGA must pay attention to when using it as a chip level. Any chip must have input pins and output pins. With programmable IO, you can arbitrarily define a certain non-dedicated pin (the FPGA has a dedicated non-user-usable test and download pin) as input or output, and you can also set the IO level standard. In a word, FPGAs are programmable because they can be made into "truth tables" through special 01 codes, and these "truth tables" can be combined to realize large-scale logic functions. Without understanding the internal structure of the FPGA, one cannot understand how the final code changes to the FPGA. There is no in-depth understanding of how to make full use of FPGAs. The current FPGA not only has the three pieces mentioned above, but also has many dedicated hardware functional units. How to make good use of these units to realize complex logic circuit design is an obstacle that must be overcome on the way from a rookie to a master. And all of this, we must first start by understanding the internal logic of the FPGA and its working principle. 2. Wrong understanding of HDL language, no hardware structure can be seen no matter how you look at it The full English name of HDL language is: Hardware Deion Language, pay attention to the word Deion, not Design. Why do foreigners use the word Deion instead of Design? Because HDL is really not used to design hardware, but only used to describe hardware. The word description accurately reflects the nature of the HDL language. HDL language is just a textual representation of known hardware circuits, and it only describes the future circuits in the form of text. Before writing the language, the hardware circuit should have been designed. Language is nothing more than transforming this design into a written form of expression. But many people don't understand. Now that the hardware has been designed, it will be done directly by the production department. Why do you need to convert it into text and then pass the troublesome process of EDA tools? In fact, this is the problem that many rookies do not understand the abstract level of design. Any design includes what clothing, machinery, and advertising design has an abstract level. Take advertising design as an example. The initial design may be a concept, and the design of this concept is just an idea. It is far from the final advertisement. Hardware design also has different levels of abstraction, and each level needs to be designed. The highest level of abstraction is the algorithm level, followed by the architecture level, register transfer level, gate level, and physical layout level. The advantage of using HDL is that we have designed a register transfer-level circuit, then the HDL description will be transformed into a text form, and the remaining conversion to a lower level can be done by the EDA tool, which is huge Reduce the workload. This is a synthesizable concept, which means that the description of hardware units at this abstract level can be understood by EDA tools and transformed into low-level gate-level circuits or circuits with other structures. In the FPGA design, this is described as an HDL language at an abstract level, and it can be transformed into the FPGA internal logic function implementation form described in Question 1 through the FPGA development software. HDL can also describe a higher level of abstraction such as algorithm level or architecture level. However, currently limited by the development of EDA software, EDA software cannot understand such a high level of abstraction. Therefore, the abstract level described by HDL cannot be transformed into At a lower level of abstraction, this is also called unsynthesizable. Therefore, when reading or writing HDL languages, especially synthesizable HDL, you should not see the language itself, but the corresponding hardware circuit structure behind the language. If the HDL you see is always a piece of code, then this kind of person will never get rid of the fate of a rookie. If one day the code you see is no longer a line of code but a piece of hardware module, then congratulations on leaving the rookie level and entering the less rookie level. 3. FPGA itself is nothing, everything is outside of FPGA. This is probably the most difficult point for many FPGA rookies to understand. Who is the FPGA for? Many schools explain that it is for students majoring in microelectronics or integrated circuit design. In fact, this is just because many schools are limited by funds and cannot afford professional integrated circuit design tools and use FPGA tools instead. In fact, FPGAs are used by engineers who design electronic systems. These engineers usually use existing chips to complete an electronic device, such as base stations, set-top boxes, and video surveillance equipment. When the existing chips cannot meet the needs of the system, FPGAs are needed to quickly define a usable chip. As mentioned earlier, there can’t be some "truth tables", flip-flops, various connections, and some hardware resources in FPGAs. When electronic system engineers use FPGAs for design, they are nothing more than considering how to combine these resources to achieve certain logic functions. That's it, instead of having to pay attention to whether the final chip can be manufactured like an IC design engineer. In essence, it is no different from using existing chips to combine into different electronic systems. It just needs to pay attention to lower-level resources. To use FPGA is still simple, because it is nothing more than those resources. After understanding the first two points, build an experiment board, run experiments, and do something simple. But if you really want to use FPGAs well, it is far from enough to understand FPGA knowledge. Because in the end, how to combine the resources in the FPGA and what functions can be implemented to meet the needs of the system, it needs to know more and more extensive knowledge. At present, the application of FPGA is mainly in three directions: The first direction, which is also the traditional direction, is mainly used for the design of high-speed interface circuits of communication equipment. This direction is mainly to use FPGA to process high-speed interface protocols and complete high-speed data transmission and exchange and exchange. This type of application usually requires the use of FPGAs with high-speed transceiver interfaces, and at the same time requires designers to understand high-speed interface circuit design and high-speed digital circuit board-level design, have EMC/EMI design knowledge, and a good analog circuit foundation. Signal integrity issues arising in the process. The most widespread application of FPGA is in the communication field at first and so far. On the one hand, the communication field requires high-speed communication protocol processing methods, and on the other hand, the communication protocol is being modified at any time, which is very unsuitable for making special chips. Therefore, FPGAs that can flexibly change functions become the first choice. So far, more than half of the applications of FPGAs are also in the communications industry. The second direction can be called the digital signal processing direction or the mathematical calculation direction, because to a large extent this direction has greatly exceeded the scope of signal processing. For example, as early as 2006, I heard that Lao Mei used FPGAs for financial data analysis, and later I saw cases where FPGAs were used for medical data analysis. In this direction, FPGA designers are required to have a certain mathematical foundation, be able to understand and improve more complex mathematical algorithms, and use various resources inside the FPGA to make them into actual arithmetic circuits. At present, what is really put into practical use is still in the fields of wireless signal processing, channel coding and decoding, and image signal processing in the communication field. Research in other fields is under way. Understand this stuff. However, it has recently been discovered that many PhDs in electronic engineering and computer science in Europe and the United States have transferred to the financial industry to carry out financial signal processing. I believe that as the number of transfers increases, the mathematical calculation functions of FPGA in other fields will be better played. I also intend to do some research in these areas. However, those who study finance and medicine in China rarely use mathematics. Needless to say, FPGA is used to help them complete mathematics. This issue can only be discussed again. The third direction is the so-called SOPC direction. In a strict sense, this is already within the scope of FPGA design. It is just the low-level hardware environment of an embedded system built on the FPGA platform, and the designer is mainly on it. It's just for embedded software development. The design time for the FPGA itself is quite small. But if it involves special algorithm acceleration in FPGA, knowledge in the second direction is actually needed, and knowledge in the first direction is needed to design a special interface circuit. At present, the development of SOPC is far inferior to the first and second directions. The main reason is that SOPC is mainly based on FPGA, or it is to implement a "soft" processor in the resources inside the FPGA, or to embed one in the FPGA. Processor core. However, most of the embedded design is based on software. Judging from the current hardware development, the interfaces in most cases have been standardized, and there is no need for such large FPGA logic resources to design too complex interfaces. Moreover, it seems that SOPC-related development tools are still very imperfect, and various embedded processor development tools represented by ARM have long been deeply rooted in the hearts of the people. Most SOC chips with ARM as the core provide most standard interfaces. A large number of single-chip microcomputers/embedded processors provide hardware acceleration circuits required by related industries, and there are indeed very few occasions where special hardware needs to be customized. Usually it is in some special industries that there is a very urgent need in this regard. Even if Xilinx adds ARM's hard core to the FPGA, I believe the current situation will not change much. Don’t forget that many old 8-bit microcontrollers are still mixed in the embedded field. The embedded system is not based on hardware differences. More depends on the difference of software to reflect the value. I used to be optimistic about the idea of ​​Psoc from cypress. Unlike the SOPC series, Psoc’s thought history contains a small piece of FPGA embedded in the SOC chip, which can actually meet the small differences in embedded hardware interfaces. For example, a certain application requires 4 USBs, while the usual processor If you don't provide so many, you can use such a piece of FPGA to provide multiple USB interfaces. While another application requires 6 UARTs, it can also be done in the same way. For embedded design companies, they only need to stock one type of chip to meet the small differences in these designs. The main differentiation is still done through software. But currently cypress is too closed, if it uses ARM as the processor core, with its complete tool chain. At the same time, it is very promising to open up IP cooperation and let a large number of third parties provide IP design for it. But the current days of cypress are not so easy, and Psoc's thoughts do not know when it will shine. 4. Knowledge of digital logic is fundamental. No matter which direction it is FPGA, it is inseparable from the support of digital logic knowledge. To put it plainly, FPGA is a way to implement digital logic. If there is a problem with even the most basic digital logic knowledge, the desire to learn FPGA is just a castle in the air. And this is precisely the problem that many rookies are most unwilling to face. Digital logic is the professional basic knowledge of any electrical and electronic major, and it is also a course that must be learned well. Many people just study, take a test, and it's over. If you can't master the knowledge of digital logic, develop good design habits, and at the end of learning FPGA, you will still be looking at the moon in the fog, and it will always be empty. The above four points are just my summary of the easiest place for novices to deviate when learning FPGA. FPGA learning is actually like learning Go. It is easy to learn how to play on a chessboard, but it is even more difficult to become a master. In order to really become a godlike player like Lee Chang-ho, in addition to relying on hard work, I'm afraid I really need a little talent. Recommended reading: How to learn FPGA? Why do you think FPGA is difficult to learn? 1. To get started, you must first master HDL (HDL=verilog+VHDL) The first sentence is: if you haven't learned the mathematics and electricity, first learn the mathematics and electricity. Then you can choose verilog or VHDL, if you have C language foundation, it is recommended to choose VHDL. Because verilog is too similar to C, it is easy to confuse, in the end you will find that you spend a lot of time to distinguish between the two languages, rather than learning how to use it. Of course, if you can turn your mind around, you can also choose Verilog. After all, Verilog is used more in China. Next, first find this example and copy the code. The significance of copying code is to be familiar with grammar rules and compilers (here the compiler is a silicon compiler and also called a synthesizer. Commonly used compilers are: Quartus, ISE, Vivado, Design Compiler, Synopsys’ VCS, iverilog, Lattice’s Diamond, Microsemi/Actel's Libero, Synplify pro), and then imitate and write, and finally can write without reading a book. After compiling the code, open the RTL diagram to see what kind of circuit is synthesized. HDL is a hardware description language, highlighting the characteristics of hardware, so you should think about HDL with digital thinking instead of C language or other high-level languages. If you can’t understand this sentence, you can read "What is hardware and what is software". At this stage, the recommended textbook is "Verilog Legend", "Verilog HDL Advanced Digital Design" or "VHDL for Logic Synthesis". You can write a three-stage state machine without reading a book and you can enter the next stage. In addition, you must prepare Verilog or VHDL official documents, "verilog_IEEE Official Standard Manual-2005_IEEE_P1364", "IEEE Standard VHDL Language_2008", so that you can check it when you encounter some grammatical problems. 2. Independently complete the design of small and medium-sized digital circuits Now, you can design some digital circuits, such as traffic lights, electronic organs, DDS, etc. The recommended textbook is Xia Lao's "Verilog Digital System Design Tutorial" (third edition). At this stage, what you have to do is: give you an index requirement or timing diagram, and you can use HDL to design a circuit to implement it. Here you need a development board, you can choose Altera's cyclone IV series, or Xilinx's Spantan 6. Don't buy a development board before you master HDL, because it's useless if you buy it back. Here you don’t need to download the code every time you compile and pass, we use modelsim to simulate (in addition to QuestaSim, NC verilog, Diamond’s Active-HDL, VCS, Debussy/Verdi and other simulation tools), if the simulation fails, then you don’t need to download it. Yes, it definitely won't work. Here you can master the simple testbench first. The recommended textbook is "WRITING TESTBENCHES Functional Verification of HDL Models". 3. Master design methods and design principles You may find that the circuit you synthesized is correct, but there are many warnings. At this time, you have to learn the principles of synchronous design, optimizing circuits, whether speed or area is the priority, how to design the clock tree, how to synchronize two clocks with different frequencies, and so on. The recommended textbooks are "FPGA Authority Guide", "IP Core Records-Digital Logic Design Thoughts", "Altera FPGA/CPLD Design" the second edition of the basic and advanced chapters. Learn to speed up compilation (incremental compilation, LogicLock), static timing analysis (timequest), and embedded logic analyzer (signaltap) even if you pass the customs. If there is something you don’t understand, you can skip it temporarily, because this part still requires a sufficient amount of practice to have a deeper understanding. 4. Learn to improve development efficiency Because the editor functions of Quartus and ISE are too weak, the development efficiency is affected. Therefore, it is recommended to use the code snippet function in the Sublime text editor to reduce repetitive work. Modelsim is also a commonly used simulation tool. Learn TCL/TK to write a DO file suitable for yourself and make the simulation automatic. The recommended textbook is "TCL/TK Introduction Classic". You may manually back up the code, but professionals use version controllers, so in order to improve work efficiency, you must master GIT. File comparator Beyond Compare is also a more commonly used tool. In addition, you can also use System Verilog instead of testbench, which will be more efficient. If you are doing IC verification, you must master System Verilog and Verification Methodology (UVM). The recommended textbooks are "Writing Testbenches using SystemVerilog", "The UVM Primer", and "System Verilog1800-2012 Grammar Manual". After mastering TCL/TK, you can learn virtual Jtag (the ISE also has similar tools) to make your own debugging tools. In addition, if you have time, it is best to learn python again. Scripting means once and for all. 5. Strengthen the theoretical foundation At this time, you already know how to use FPGA, but there are still many things you can't do (for example, FIR filter, PID algorithm, OFDM, etc.) because the theory is not well studied. I roughly divide it into several directions for your reference, followed by theoretical lessons to be mastered. Signal processing-signal and system, digital signal processing, digital image processing, modern digital signal processing, blind signal processing, adaptive filter principle, radar signal processing Interface applications-such as: UART, SPI, IIC, USB, CAN, PCIE, Rapid IO, DDR, TCP/IP, SPI4.2 (10G Ethernet interface), SATA, optical fiber, DisplayPort Wireless communication-signals and systems, digital signal processing, communication principles, basics of mobile communication, random processes, information theory and coding CPU design-computer composition principle, single-chip microcomputer, computer architecture, compilation principle Instrumentation-analog electronic technology, high-frequency electronic circuits, electronic measurement technology, principles and applications of intelligent instruments Control system-automatic control principle, modern control theory, process control engineering, fuzzy controller theory and application Compression, coding, encryption-number theory, abstract algebra, modern coding technology, information theory and coding, introduction to data compression, applied cryptography, audio information processing technology, digital video coding technology principle Now you find that FPGA will involve so much knowledge, you can choose a direction of interest, but it is very likely that you will use knowledge in several directions in your work, so the more you learn the theory, the better. If you want to take it to the next level, mathematics and English are inevitable. 6. Learn to use MATLAB simulation When designing FPGA algorithms, MATLAB is used more or less, such as CRC coefficient matrix, digital filter coefficients, various tables and text processing. In addition, MATLAB can also be used to debug HDL (compare the calculation results with MATLAB and HDL step by step to know where the problem is). The recommended textbooks are "The Collection of MATLAB" and "The Realization of Digital Filters in MATLAB and FPGA" by Du Yong. 7. Sufficient practice At this time, you have read the chip manual at least a few times (the official website has it), and then you can do a certain amount of practice in your own direction (in the meantime, you must maintain a good code style, increase the readability of component instantiation statements, and draw a flowchart / Timing diagram, the habit of writing documents). For example: communication type can be used as modulation and demodulation algorithm, instrument type can be used as bus analyzer and so on. However, these algorithms are just formulas and block diagrams in the book, which are far from the actual ones, and you may even think that the things in the book are very superficial. Then, you can find relevant information on HowNet, Baidu Library, EETOP forums, opencores, ChinaAET, Q group sharing, and blogs (friends outside school can buy a CNKI account on Taobao). In fact, when you get to this stage, you have reached the professional level. You can learn more about cutting-edge technologies when you have time, which will help your career planning. In your work, you may need to pay attention to many protocols and industry standards. The protocols can be found on EETOP, and standards (such as national standards GB and GB/T, international standards ISO) recommend the "standard network" and "standard sharing network" . 8. Image processing (this part is only for friends who want to learn image processing, it is also a route from shallow to deep) Photoshop. Spend one or two weeks to learn PS, have a general understanding of image processing, know the basic concepts of various image formats, histograms, hue, channels, filters, stitching, etc., and be able to use it. This part is a zero foundation, and the purpose is to give everyone a perceptual understanding of image processing, rather than deriving various formulas from the beginning. Recommend "Photoshop CS6 Complete Self-study Tutorial". Image processing based on MATLAB or OpenC++V. Those who have C/C++ foundation can learn OpenCV, otherwise, it is recommended to learn MATLAB. At this stage, as long as you learn to simply call the function, you don't need to go into the details of the implementation for the time being. Recommend "digital image processing matlab version", "learning OpenCV". The basic theory of image processing. This part of the theory requires basics such as high numbers, complex variables, linear algebra, signals and systems, and digital signal processing. If the basics are not good, it is recommended to supplement the basics first. Theories that you don’t understand can also be put aside for the time being, and maybe you will learn them later. Recommend "Digital Image Processing". FPGA-based image processing. Apply the theory learned before to FPGA, if you have the level of the seventh stage, you will easily complete the image algorithm design independently (image processing is inseparable from the interface, the fifth stage above is about ). Recommend "Design of Embedded Image Processing System Based on FPGA", "Principle and Application of Digital Image Processing Based on FPGA". Delve further into mathematics. To get a higher level of algorithm, more mathematics is inevitably needed, so it is recommended to learn real analysis, general analysis, wavelet analysis and so on. The following two stages are introduced to interested friends. 9. The end of the digital power is the analog power Now things inside the FPGA can’t be bothering you, but if the signal goes out of the FPGA, you can’t control it. At this time, we must learn to model electricity well. For example: circuit analysis, analog electronic technology, high-frequency electronic circuits, PCB design, EMC, SI, PI, etc., if you can design an FPGA development board with two DDR3 chips, even if you pass the customs. 10. Learning is endless Being able to reach this level means that you are already very good, but there is still a lot to learn, because FPGAs often have to interact with the CPU, which means that you have to communicate with software engineers frequently, so you have to understand some software knowledge. For example, ARM (Xilinx's ZYNQ and Altera's SOC will use ARM's hard core), DSP, Linux, Android, upper computer (QT, C#, JAVA) can all learn it, anyway, there is no end to learning. 11. Other issues a. Why is it not recommended to learn soft cores such as NIOS II and MicroBlaze? The price/performance ratio is not high. The general soft core performance is about the same as Cortex M3 or M4. It is not cost-effective in engineering to use something as expensive as FPGA to make a CPU with general performance. It is better to add another piece of M3. Adding the soft core may affect other logic functions. This is in the case of insufficient resources, coupled with the soft core, which makes it quite difficult to place and route. Soft cores are not open source, and when there are bugs, it is not easy to debug. It is rarely used in engineering, and it is very likely that it will not come in handy. b. Why not recommend zero-based learning ZYNQ or SOC? It is easy for people to have the same psychology. The same psychology means that a person can conceal and make up for his shortcomings in this respect by exaggerating the excellence of those close to him, so as to obtain a psychological balance. I am learning something great, and then I feel great, but this is just an illusion. Getting started should learn as simple as possible, either concentrate on learning ARM, or concentrate on learning FPGA. This makes it easier to have a sense of accomplishment and enhance confidence. The application areas of ZYNQ and SOC are not wide, and there are still many people who have not heard of such things, which leads to disadvantages in job hunting. Development tools take a long time to compile and waste a lot of time. Most of the work is only responsible for one aspect, that is to say, on the other hand, it is very likely that it will not come in handy. c. Why do we still need to write HDL with so many IP cores? The students who ask this kind of question are usually students who have never made a product or encountered engineering problems. IP cores are not omnipotent and cannot meet all needs. Try to minimize the use of closed-source IP cores. Once a problem occurs, this black box is likely to make the product difficult to produce. To understand the bottom level deeply, you can use the higher level better. This rule can be applied to all programming languages. Hybrid IP65 Solar Power Inverter Shenzhen Jiesai Electric Co.,Ltd , https://www.gootuenergy.com